Forging Tomorrow's Silicon
Transforming complex logic into manufacturable silicon.
Physical Design Expert • ASIC Manager • Semiconductor Leader
Silicon Delivered
26+
Tape-outs delivered
7nm → 180nm
Multi-node experience
2GHz
Timing closure expertise
21
Engineers mentored
PNR + STA + EMIR + PV
Full ownership
§Expertise
End-to-End Physical Design
RTL → GDSII
PNR / CTS / STA / Timing Closure
SI / EMIR / PV Signoff
Power, Performance, Area Optimization
TCL / Perl Automation
Leadership & Delivery Execution
Silicon Insights
Articles on Physical Design, Timing Closure & Semiconductor Leadership
Physical Design Concepts Covered
by challakcr / October 18, 2025
Modules in this discussion
What is Physical Design?
by challakcr / October 18, 2025
I've created a comprehensive VLSI Physical Design Course document that covers the complete backend design flow from RTL to GDSII...
Welcome to My Technical Blog
by challakcr / October 18, 2025
Here is a professionally rewritten, story-driven introduction for your website, structured to highlight your journey and impact...